(1) Field of the Invention
The present invention relates to a method used to increase the surface area of a capacitor structure, used for a dynamic random access memory, (DRAM) devices.
(2) Description of the Prior Art
Improved device performance and the reduced manufacturing costs of these devices, are major objectives of the semiconductor industry. These objectives have been successfully addressed by the ability of the semiconductor industry to fabricate semiconductor memory chips with sub-micron features, or microminiaturization. Sub-micron features allow the reduction in performance degrading capacitances and resistances to be realized. In addition the smaller features result in a smaller chip, however still possessing the same level of integration obtained for semiconductor chips fabricated with larger features. This allows a greater number of the denser, smaller chips to be obtained from a specific size starting substrate, thus resulting in a lower manufacturing cost for an individual chip.
The use of smaller, or sub-micron, features, when used for the fabrication of dynamic random access memory, (DRAM), devices, in which the capacitor of the DRAM device is a stacked capacitor, (STC), or crown, structure, presents difficulties when attempting to increase STC capacitance. A DRAM cell is usually comprised of the STC structure, overlying a transfer gate transistor, and connected to the source of the transfer gate transistor. However the decreasing size of the transfer gate transistor, limits the dimensions of the STC structure. To increase the capacitance of the STC structure, comprised of two electrodes, separated by a dielectric layer, either the thickness of the dielectric layer has to be decreased, or the area of the capacitor has to be increased. The reduction in dielectric thickness is limited by increasing reliability and yield risks, encountered with ultra thin dielectric layers. In addition the area of the STC structure is limited by the area of the underlying transfer gate transistor dimensions. The advancement of the DRAM technology to densities of 64 million cells per chip, or greater, has resulted in a specific cell in which a smaller transfer gate transistor is being used, resulting in less of an overlying area for placement of overlying STC structures.
One method of maintaining, or increasing STC capacitance, while still decreasing the lateral dimension of the capacitor, has been the use of rough, or hemispherical grain, (HSG), silicon layers. HSG silicon layers have been used as an overlying layer, on a conventional polysilicon structure, as shown by Dennison, in U.S. Pat. No. 5,340,763, and by Nagasawa, et al, in U.S. Pat. No. 5,444,653. The convex and concave features of the HSG silicon layer result in increases in capacitor surface area, without consuming additional device area, thus resulting in DRAM capacitance increases, when compared to counterparts fabricated with smooth capacitor surfaces. However several factors have limited the use of HSG layers, for DRAM applications. The presence of an unwanted thin native oxide, on an underlying polysilicon capacitor surface, can result in poor adhesion between the subsequent HSG silicon layer, and the underlying polysilicon capacitor. The unwanted native oxide can also interfere with the selective deposition of HSG silicon, when deposition is only desired on underlying polysilicon surfaces, not on neighboring insulator surfaces. To alleviate the effect of the thin native oxide a high vacuum, in situ cleaning procedure, has to be used prior to HSG silicon deposition. The need for high vacuum, native oxide removal, requires a specific tool, different from the system used for HSG seeding and formation, thus increasing process cost and complexity.
This invention will describe a process for creating HSG silicon, in a conventional low pressure chemical vapor deposition, (LPCVD), system, featuring an hydrofluoric, (HF), vapor pre-clean, performed in a low pressure chamber, of a cluster tool, transfer of the semiconductor wafers, in nitrogen environment, to an LPCVD chamber, in the cluster tool, followed by a selective HSG seeding procedure, and by a selective HSG and formation procedure, both performed in the same LPCVD system at a pressure less than 1 Torr, thus avoiding the need for more costly equipment, that would be necessary if a pressure in the range of 10.sup.-8 torr were to be used.